Electronic ballast having adaptive frequency shifting

ABSTRACT

An electronic ballast for driving a gas discharge lamp avoids mercury pumping in the lamp by adaptively changing an operating frequency of an inverter of the ballast when operating near high-end. The inverter of the ballast generates a high-frequency AC voltage, which is characterized by the operating frequency and an operating duty cycle. The ballast also comprises a resonant tank for coupling the high-frequency AC voltage to the lamp to generate a present lamp current through the lamp, and a current sense circuit for determining the magnitude of the present lamp current. A hybrid analog/digital control circuit controls both the operating frequency and the operating duty cycle of the inverter with closed-loop techniques. The control circuit adjusts the duty cycle of the inverter in response to a target lamp current and the present lamp current. To avoid mercury pumping, the control circuit attempts to maximize the duty cycle of the inverter when operating at high-end. Specifically, the control circuit adjusts the operating frequency of the inverter in response to the target lamp current signal, the duty cycle of the inverter, and a target duty cycle in order to drive the operating duty cycle toward the target duty cycle.

FIELD OF THE INVENTION

The present invention relates to electronic ballasts and, moreparticularly, to electronic dimming ballasts for gas discharge lamps,such as fluorescent lamps.

BACKGROUND OF THE INVENTION

Electronic ballasts for fluorescent lamps typically can be analyzed ascomprising a “front-end” and a “back-end”. The front-end typicallyincludes a rectifier for changing alternating-current (AC) mains linevoltage to a direct-current (DC) bus voltage, and a filter circuit,e.g., a capacitor, for filtering the DC bus voltage. The front-end ofelectronic ballasts also often includes a boost converter, which is anactive circuit for boosting the magnitude of the DC bus voltage abovethe peak of the line voltage and for improving the total harmonicdistortion (THD) and the power factor of the input current to theballast. The ballast back-end typically includes a switching inverterfor converting the DC bus voltage to a high-frequency AC voltage, and aresonant tank circuit having a relatively high output impedance forcoupling the high-frequency AC voltage to the lamp electrodes.

Referring first to FIG. 1, there is shown a simplified block diagram ofa prior art electronic ballast 100. The ballast 100 includes a front-end102 for producing a substantially DC bus voltage across a bus capacitor,C_(BUS), from an AC input voltage. The ballast 100 further comprises aninverter 104 for converting the DC bus voltage into a high-frequencyvoltage for driving a lamp current in a fluorescent lamp 108. Thehigh-frequency voltage provided by the inverter 104 is coupled to thelamp 108 through a resonant tank 106 having a resonant inductor,L_(RES), and a resonant capacitor, C_(RES).

The inverter 104 includes first and second series-connected switchingdevices 112, 114 and a gate drive circuit 116. The switching devices112, 114 in the inverter 104 are controlled using a d(1−d) complementaryswitching scheme. In the d(1−d) complementary switching scheme, thefirst switching device 112 has a duty cycle of d and the secondswitching device 114 has a duty cycle of 1−d. The switching devices 112,114 are controlled by the gate drive circuit 116 such that only oneswitching device is conducting at a time. When the first switchingdevice 112 is conducting, then the output of the inverter 104 is pulledupwardly toward the DC bus voltage. When the second switching device 114is conducting, then the output of the inverter 104 is pulled downwardlytoward circuit common.

The current through the lamp 108 is controlled by changing the frequencyand/or the duty cycle of the high-frequency voltage at the output of theinverter 104. A current sense circuit 110 is coupled in series with thelamp 108 and provides a lamp current signal 250 representative of themagnitude of the current through the lamp. An analog control circuit 210is responsible for controlling the gate drive circuit 116 and thus theswitching devices 112, 114 of the inverter 104. The analog controlcircuit 210 includes a reference circuit 212, a summing circuit 214, acompensator circuit 216, a frequency-shift circuit 218, a triangle-waveoscillator 222, and a comparator 220. The reference circuit 212 providesa reference signal 242 representative of a target current I_(TARGET) forthe lamp 108. The summing circuit 214 receives the lamp current signal250 and the reference signal 242 and creates an error signal 240representative of the difference between the target current and theactual current in the lamp 108. The compensator circuit 216 receives theerror signal 240 and provides a duty cycle request voltage 246 that isproportional to the desired duty cycle of the inverter 104.

The frequency shift circuit 218 also receives the reference signal 242and provides a desired frequency signal 245 representative of thedesired inverter frequency. The triangle-wave oscillator 222 receivesthe desired frequency signal 245 from the frequency shift circuit 218and provides a triangle-wave signal 244 at the desired frequency. Thecomparator 220 receives both the triangle wave signal 244 and the dutycycle request voltage 246 and produces a pulse width modulated (PWM)signal 248 with the desired frequency and duty cycle. This PWM signal248 is provided to the gate drive circuit 116, which drives the switches112, 114 in the inverter 104.

In addition to the normal running mode, the ballast 100 has severalother modes of operation including a “preheat” mode and a “strike” mode.The purpose of the preheat mode is to heat the lamp filaments prior tothe application of a sufficient voltage to strike the lamp. During thestrike mode, the lamp voltage is increased until either the lamp strikesor a predetermined voltage limit is reached.

Preheat is accomplished by controlling the frequency of the inverter 104to a preheat frequency, which is greater than the frequency of theinverter 104 in normal operation. During preheat, the compensatorcircuit 216 is always in control of the duty cycle of the inverter 104.At the same time, the reference circuit 212 provides a reference signal242 at a level that represents a non-zero lamp current. Since there isno current through the lamp during preheat, the current sense circuit110 produces the lamp current signal 250 with a positive magnitude andthus the output of the summing circuit 214, i.e., the error signal 240,has a non-zero value. The compensator circuit 216 includes an integrator(not shown), so the non-zero error signal 240 causes the compensatorcircuit 216 to increase the duty cycle of the duty cycle request voltage246 to 50%, at which time the compensator circuit saturates. At thispoint, the duty cycle of the duty cycle request voltage 246 is fixed at50% and the preheat voltage is adjusted by changing the frequency. It isimportant to note that since the compensator circuit 216 contains anintegrator, it is not possible to set the duty cycle to an arbitrarylevel. In practice, the choices would be saturated at 50% or saturatedat 0%. An alternative would be to provide additional circuitry to clampthe output of the compensator circuit 216 at a given level duringpreheat, but this would add additional cost and complexity.

To strike the lamp 108, i.e., in the strike mode, the operatingfrequency of the inverter 104 is swept down from the preheat frequencyto a low-end frequency. Preferably, the low-end frequency is near theresonant frequency ω_(R) of the resonant tank 106, i.e.,ω_(R)=1/√{square root over ((L_(RES)*C_(RES)))}. Accordingly, thevoltage at the output of the resonant tank 106 at the low-end frequencyis substantially large and is appropriate to strike the lamp 108. Whenthe lamp 108 strikes, the lamp current begins to flow through the lamp.At this time, the compensator circuit 216 of the analog control circuit210 is still saturated and the duty cycle of the duty cycle requestvoltage 246 is still 50%. As a result, a current above the targetcurrent starts to flow through the lamp 108. This excess current willcause the compensator circuit 216 to come out of saturation and to setthe duty cycle of the PWM signal 248 so as to maintain the targetcurrent in the lamp 108. While the compensator circuit 216 is saturated,the current in the lamp 108 can be significantly higher than the targetcurrent. The high current, along with the time required for the loop tocome out of saturation, can result in a noticeable flash when the lampsstrike.

A simplified schematic diagram of another prior art electronic ballast300 is shown in FIG. 2. The ballast 200 operates in a similar manner asthe ballast 100 shown in FIG. 1, but the analog control circuit 210 hasbeen replaced by a digital control circuit 310. An analog-to-digitalconverter (ADC) 352 in a microprocessor 350 receives the lamp currentsignal 250 from the current sense circuit 110 and converts it into an8-bit digital representation. The reference signal 242 representative ofthe target current in the lamp 108 is received at an input 355. Thesoftware in the microprocessor 350 then compares the measured currentwith the target current to generate an error signal, which is then usedto generate a desired duty cycle. The desired frequency is determinedfrom the desired current. A pulse-width modulated (PWM) signal 356 isproduced at an output 354 of the microprocessor 350. The software in themicroprocessor 350 drives the PWM signal 356 with the desired frequencyand duty cycle and provides the PWM signal to the gate drive circuit116. In the ballast 300, software in the microprocessor 350 of thedigital control circuit 310 provides the functionality that was providedby the analog control circuit 210 of the ballast 100.

The digital implementation of the preheat mode of the ballast 300 isvery different than the preheat mode of the ballast 100. The softwarethat normally implements the compensator routine is not in control ofthe inverter duty cycle. In fact, a completely different routine is incontrol of the inverter. As a result, it is possible to directly controlboth the duty cycle and the frequency to achieve the desired preheatlevel.

In the digital implementation of the strike mode, the duty cycle is heldat a fixed level and the frequency is swept down from the preheatfrequency to the low-end frequency. During this period, the softwaremust monitor the lamp voltage and lamp current to detect when the lampstrikes. It is very important to detect when the lamp strikes becauseonce it is struck, a different routine must be run to implement thenormal operation control loop. Since both the frequency and duty cycleare controllable during strike, it would be possible to set the dutycycle to something less than 50% during the strike phase. The lower dutycycle would result in the lamp starting at a lower current to helpreduce flash. However, in order to ensure accurate detection of lampstrike, the lamp must strike with a relatively high current.

Replacing the analog control circuit 210 of the ballast 100 with thedigital control circuit 310 of the ballast 300 has several benefits.First, there are fewer parts in the digital control circuit 310 sincemost of the control functions are completed by the microprocessor 350.Second, the control functions provided by the microprocessor 350 can beeasily altered without the need to change any hardware of the digitalcontrol circuit 310. Further, situation-specific software can beexecuted when the ballast 300 is in different normal and abnormal modesof operation.

However, the digital control circuit 310 has some disadvantages in viewof the analog control circuit 210. The capability of the microprocessor350 is dependent on the cost of the device. So, in order to achieve areasonable cost, some compromises may need to be made in the areas ofcore speed, ADC resolution, ADC sampling rate and math capability.Quantization effects of the ADC conversion can become significant at lowdim levels. This can be improved with a higher resolution ADC or ahigher sampling rate, but as mentioned earlier, higher capabilityresults in higher cost for the microprocessor 350.

Both the analog control circuit 210 and the digital control circuit 310of the prior art ballast 100, 300 use an open-loop frequency shift inwhich there is a predetermined operating frequency for a given desiredlight level. The concept of adjusting both the frequency and the dutycycle of the inverter 104 is described in greater detail in U.S. Pat.No. 6,452,344, issued Sep. 17, 2002, entitled “Electronic DimmingBallast”, which is hereby incorporated herein by reference in itsentirety.

FIG. 3 is a simple control system diagram illustrating the control loopsof the prior art ballasts 100, 300. The operating duty cycle, d_(OP), ofthe inverter is controlled through a closed-loop technique, while theoperating frequency, f_(OP), is controlled through an open-looptechnique. The actual lamp current, I_(ACTUAL), is provided as feedbackto the duty-cycle control loop and is subtracted from the targetcurrent, I_(TARGET), to produce a lamp current error signal, e_(I), andultimately, the desired operating duty cycle d_(OP). In contrast, thedesired operating frequency f_(OP) is simply generated solely inresponse to the target current I_(TARGET).

FIG. 4 shows a plot of the target operating frequency of the inverter104 versus the lamp current and a plot of the operating frequency versusthe lamp current at a fixed 50% duty cycle, which demonstrates themaximum current that can be delivered by the ballast 100, 300 at a givenfrequency. At low light levels, the ballast operating frequency ismaintained at the low-end frequency f_(LOW-END), which is near theresonant frequency of the resonant tank 106. Above a predeterminedlevel, the operating frequency is decreased linearly as the lamp currentincreases, i.e., as the desired lighting level of the lamp 108 increasestowards high-end.

One complication that results from operating the inverter 104 at afrequency that is away from the resonant frequency when utilizing thed(1−d) switching scheme (i.e., at high-end) is the possibility of“mercury pumping”. As the operating frequency moves away from theresonant frequency, and the impedance of the lamp 108 decreases (as thelamp current increases), the filtering effect of the resonant tank 106is reduced. When the inverter 104 is operating at any duty cycle otherthan 50%, the voltage at the output of the inverter is asymmetric andcontains second harmonic content. For duty cycles near 50%, the secondharmonic is not significant. However, as the duty cycle moves away from50%, the second harmonic content increases.

When operating at the high-end frequency f_(HIGH-END), a significantamount of this second harmonic content from the inverter 104 is passedthrough the resonant tank 106 to the lamp 108. As a result, the lampcurrent is not symmetric. Blocking capacitors, e.g., capacitor 118 inFIGS. 1 and 2, at the output of the ballast 100, 300 prevent the ballastfrom delivering significant DC current to the lamp 108. However, theasymmetric current in the lamp 108 coupled with the non-linear lamp loadresults in a DC voltage on the lamp 108. The DC voltage on the lamp 108will cause mercury ions to migrate from one end of the lamp to theother. If the DC voltage is high enough, the lamp 108 will becomestarved for mercury at one end. As a result, the starved end of the lamp108 will produce less light and may also turn pink.

In order to avoid significant mercury pumping, the analog controlcircuit 210 and the digital control circuit 310 of the prior artballasts 100, 300 utilized frequency shift profiles that were selectedto insure that the duty cycle was as close to 50% as possible whenoperating at the high-end frequency. However, the tolerances of thecomponents of the resonant tank 106, and the variations in the operatingcharacteristics of common fluorescent lamps, require that the frequencybe selected such that even worst-case combinations are capable ofreaching the needed high-end current I_(HIGH-END). The constraints ofbeing able to reach high-end in the worst case while having the highestduty cycle possible result in the need for tight tolerances oncomponents and the need to tailor tank component values to a narrow loadrange.

Thus, there exists a need for an electronic ballast that avoids mercurypumping and operates at high-end with a duty cycle close to 50% and hasa broad range of load types, but does not require a resonant tank thathas components with small tolerances.

SUMMARY OF THE INVENTION

According to the present invention, an electronic ballast for driving agas discharge lamp includes an inverter, a resonant tank, a controlcircuit, and a current sense circuit. The inverter converts asubstantially DC bus voltage to a high-frequency AC voltage having anoperating frequency and an operating duty cycle. The resonant tankcouples the high-frequency AC voltage to the lamp to generate a presentlamp current through the lamp. The control circuit is operable tocontrol the operating frequency and the operating duty cycle of thehigh-frequency AC voltage of the inverter. The current sense circuitprovides to the control circuit a present lamp current signalrepresentative of the present lamp current. The control circuit isoperable to control the operating duty cycle of the high-frequency ACvoltage of the inverter in response to a target lamp current signal andthe present lamp current signal. Further, the control circuit isoperable to control the operating frequency of the high-frequency ACvoltage of the inverter in response to the operating duty cycle and atarget duty cycle, such that the control circuit is operable to minimizethe difference between the operating duty cycle and the target dutycycle. Preferably, the control circuit is further operable to controlthe operating frequency to a base operating frequency in dependence onthe target lamp current signal, when the target lamp current changes invalue.

The present invention further provides a method for controlling anelectronic ballast for driving a gas discharge lamp. The ballastcomprises an inverter characterized by an operating frequency and anoperating duty cycle. The method comprises the steps of generating apresent lamp current through the gas discharge lamp in response to theoperating frequency and the operating duty cycle of the inverter;generating a present lamp current signal representative of the presentlamp current; receiving a target lamp current signal representative of atarget lamp current; controlling the duty cycle of the inverter inresponse to the target lamp current signal and the present lamp currentsignal; and controlling the operating frequency of the inverter inresponse to the target lamp current signal, the operating duty cycle ofthe inverter, and a target duty cycle, such that the difference betweenthe operating duty cycle and the target duty cycle is minimized.

In addition, the present invention provides a control circuit for anelectronic ballast having an inverter for driving a gas discharge lamp.The control circuit is operable to control an operating frequency and anoperating duty cycle of the inverter of the ballast. The control circuitcomprises a duty cycle control portion for controlling the operatingduty cycle of the inverter in response to a target lamp current signaland a present lamp current signal, and a frequency control portion forcontrolling the operating frequency of the inverter in response to thetarget lamp current signal, the operating duty cycle, and a target dutycycle. The difference between the operating duty cycle and the targetduty cycle is minimized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified schematic diagram of a prior art electronicballast having an analog control circuit;

FIG. 2 is a simplified schematic diagram of a prior art electronicballast having a digital control circuit;

FIG. 3 is a simplified control system diagram illustrating the controlloops of the prior art ballasts of FIGS. 1 and 2;

FIG. 4 is a plot of the operating frequency of an inverter of theelectronic ballast of FIGS. 1 and 2 versus the lamp current;

FIG. 5A is a simplified schematic diagram of an electronic ballastaccording to the present invention;

FIG. 5B is a simplified schematic diagram of the electronic ballast ofFIG. 5A;

FIGS. 6A and 6B are flowcharts of the software executed by amicroprocessor of the ballast of FIG. 5A according to the presentinvention;

FIG. 6C is a flowchart of the software executed by the microprocessor ofthe ballast of FIG. 5A in response to a change in a target lamp current;

FIG. 7 shows a plot of the operating frequency of the electronic ballastof FIG. 5A according to the present invention;

FIG. 8 is a control system diagram illustrating the control loops of theballast according to a first embodiment of the present invention of FIG.5A;

FIG. 9 is a control system diagram illustrating the control loops of asecond embodiment of the ballast of the present invention;

FIG. 10 is a flowchart of the software executed by a microprocessor ofthe ballast of FIG. 9 according to a second embodiment of the presentinvention; and

FIG. 11 is a simplified schematic diagram of a ballast according to athird embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The foregoing summary, as well as the following detailed description ofthe preferred embodiments, is better understood when read in conjunctionwith the appended drawings. For the purposes of illustrating theinvention, there is shown in the drawings an embodiment that ispresently preferred, in which like numerals represent similar partsthroughout the several views of the drawings, it being understood,however, that the invention is not limited to the specific methods andinstrumentalities disclosed.

FIG. 5A shows a simplified block diagram of an electronic ballast 400according to the present invention. The ballast 400 includes manysimilar blocks as the prior art ballasts 100, 300, which each have thesame function as described previously. However, those components of theballast 300 that differ from the prior art ballast 100 will be describedin greater detail below.

The ballast 400 includes a hybrid analog/digital control circuit 410.The hybrid control circuit 410 improves on the characteristics of theanalog control circuit 210 and digital control circuit 310 of the priorart ballasts 100, 300. The hybrid control circuit 410 includes thesumming circuit 214 and the compensator circuit 216, which function thesame as those circuits in the prior art ballast 100.

The hybrid control circuit 410 further comprises a microprocessor 450,which provides a PWM signal 456 at an operating frequency, f_(OP), andan operating duty cycle, d_(OP), to the gate drive circuit 116 of theinverter 104. The microprocessor 450 receives a target lamp current,I_(TARGET), via an input 455. The target lamp current I_(TARGET) may beobtained, for example, from a phase-control input (not shown) or from adigital message received from a communication link (not shown). Aballast operable to receive a phase-control input is described ingreater detail in the previously mentioned U.S. Pat. No. 6,452,344. Aballast operable to be coupled to a digital communication link isdescribed in greater detail in co-pending U.S. patent application Ser.No. 10/824,248, Publication No. 2005/0179404, filed Apr. 14, 2004,entitled “Multiple-Input Electronic Ballast with Processor”, which ishereby incorporated herein by reference in its entirety.

The microprocessor 450 provides a PWM reference signal 460, having aduty cycle dependent on the target lamp current I_(TARGET), at an outputport 458. A low pass filter 462 generates a DC reference signal 464,which is representative of a desired current in the lamp 108, from thePWM reference signal 460. The summing circuit 214 receives the presentlamp current signal 250 and the DC reference signal 464 and creates alamp current error signal 440 representative of the difference betweenthe target current and the actual current in the lamp. The compensatorcircuit 216 receives the error signal 440 and provides a duty cyclerequest signal 446, which is a DC voltage inversely proportional to thedesired duty cycle of the inverter 104.

FIG. 5B is a simplified schematic diagram of the electronic ballast 400showing the current sense circuit 110 and the hybrid control circuit 410in greater detail. During the negative portions of the AC currentthrough the lamp 108, the lamp current flows through a resistor R570 anda diode D572. Alternatively, the lamp current flows through only a diodeD574 to circuit common during the positive portions of the lamp current.A resistor R576 and a capacitor C578 filter the voltage produced acrossthe resistor R570 and generate the lamp current signal 250. Accordingly,the lamp current signal 250 provides a substantially DC voltage having anegative magnitude representative of the current through the lamp 108.

The PWM reference signal 460 provided at the output port 458 of themicroprocessor 450 is filtered by the low pass filter 462 comprising aresistor R580 and a capacitor C582 to produce the DC reference signal464 representative of the target lamp current I_(TARGET). The DCreference signal 464 and the lamp current signal 250 are provided to theinverting input of an operational amplifier (op amp) 584 throughresistors R586 and R588, respectively. A DC offset voltage V_(OFFSET) isprovided to the non-inverting input of the op amp 584. A capacitor C590is connected between the inverting input and the output of the op amp584 to provide the integration functionality of the compensator circuit216. Accordingly, the output of the op amp 584 is a function of theintegral of the sum of the DC reference signal 464 and the lamp currentsignal 250. Finally, the voltage at the output of the op amp 584 isfiltered by a resistor R592 and a capacitor C594 to provide the dutycycle request signal 446 to the microprocessor 450.

FIGS. 6A and 6B are flowcharts of the software executed cyclically bythe microprocessor 450 of the ballast 400 in order to adaptively changethe operating frequency f_(OP) of the inverter 104 according to thepresent invention. The flowcharts of FIGS. 6A and 6B will be describedwith reference to the schematic diagram of the ballast 400 of FIG. 5A.Preferably, the process of FIGS. 6A and 6B repeats every 104 μsec.

An ADC 452 in the microprocessor 450 receives the duty cycle requestsignal 446 and converts the signal into a digital value (at step 502).Since the duty cycle request signal 446 is inversely proportional to theoperating duty cycle d_(OP), the microprocessor 450 inverts and scalesthe digital value to generate the operating duty cycle d_(OP). Forexample, the operating duty cycle d_(OP) is linearly scaled such that adigital value of 0 corresponds to an operating duty cycle of 0% and adigital value of 512 corresponds to an operating duty cycle of 100%. Innormal operation, the software in the microprocessor 450 uses theoperating duty cycle d_(OP) along with the operating frequency f_(OP) tocalculate an operating period, T_(OP), and an on-time, t_(ON). Theoperating frequency f_(OP) is determined from the target lamp currentI_(TARGET) and the operating duty cycle d_(OP), as will be described ingreater detail below. The operating period T_(OP) and the on-time t_(ON)are used by a PWM module 454 to provide the PWM signal 456 at theoperating frequency f_(OP) and the operating duty cycle d_(OP). Themicroprocessor 450 is operable to set the operating duty cycle d_(OP) aseither the duty cycle provided by the duty cycle request signal 446 orsome other duty cycle.

While in normal operation, the microprocessor 450 monitors the presentoperating duty cycle d_(OP) of the inverter 104. The operating dutycycle d_(OP) is subtracted from a predetermined target duty cycle,d_(TARGET), e.g., preferably 43%, to obtain a duty cycle error value,e_(d) (at step 504). If the error value e_(d) is inside of a dead-band(at step 506), the process loops around to read the duty cycle requestsignal 446 again. The dead-band is a range through which the error valuee_(d) can be varied without initiating a response in order to preventoscillations. The dead-band is preferably 1% above and below thepredetermined target duty cycle d_(TARGET), e.g., 42% to 44%. If theduty cycle error value e_(d) is outside of the dead-band, the errorvalue is then limited to a maximum positive error value, e_(MAX+), e.g.,2%, or a maximum negative error value, e_(MAX−), e.g., −2%, (at step510) in dependence on the sign of the error value. For example, if theerror value e_(d) is −2.5%, the error value e_(d) will be limited to−2%.

Next, the error value e_(d) is added to a 16-bit accumulator ACC in themicroprocessor 450, thereby increasing (or decreasing) the value of theaccumulator (at step 512). When the accumulator reaches a predeterminedpositive value (or a predetermined negative value), the microprocessor450 will reset the accumulator and change the operating frequency f_(OP)of the ballast (as described in greater detail below). Accordingly, ifthe error value e_(d) is large, the accumulator will reach thepredetermined positive (or negative) value more quickly. Preferably, thepredetermined positive and negative values correspond to the size of theaccumulator, e.g., +(2¹⁶−1) and −(2¹⁶−1), respectively, for the 16-bitaccumulator ACC. The accumulator reaches the predetermined positivevalue (or the predetermined negative value) when the accumulatoroverflows. The microprocessor 450 acts on the overflow of theaccumulator by reading a carry flag (which is set when the accumulatoroverflows) and a negative flag (which is set when the accumulator has anegative value). When the accumulator overflows, the value of theaccumulator is automatically reset to zero. The accumulator is alsoreset to zero at the startup of the microprocessor 450.

Referring to FIG. 6B, if the duty cycle is above (or below) thepredetermined target duty cycle d_(TARGET), the microprocessor 450 willslowly decrease (or increase) the operating frequency f_(OP) of theinverter 104, thereby decreasing (or increasing) the required duty cycled_(OP) to deliver the present target lamp current I_(TARGET). Themicroprocessor utilizes a correction factor, CF, to generate theoperating period T_(OP), and thus the operating frequency f_(OP), of theinverter 104. Preferably, the operating period T_(OP) is equal to thebase period T_(BASE) plus the correction factor CF, i.e.,

$\begin{matrix}{f_{OP} = {\frac{1}{T_{BASE} + {CF}}.}} & \left( {{Equation}\mspace{20mu} 1} \right)\end{matrix}$The correction factor CF is initialized to zero at the startup of themicroprocessor as well as each time the lamp 108 is struck.

When the duty cycle d_(OP) is above the predetermined target duty cycled_(TARGET), i.e., the accumulator ACC has exceeded the predeterminedpositive value (at step 514), the microprocessor 450 increases thecorrection factor CF (at step 516) by a predetermined increment, e.g.,preferably 0.125 μsec, which corresponds to a frequency shift of about252 Hz when the operating frequency f_(OP) is 45 kHz, and a frequencyshift of about 607 Hz when the operating frequency f_(OP) is 70kHz. Thecorrection factor CF then is limited to a maximum correction factorCF_(MAX) (at step 518). If the duty cycle d_(OP) is below thepredetermined target duty d_(TARGET), i.e., the accumulator ACC hasexceeded the predetermined negative value (at step 520), themicroprocessor 450 decreases the correction factor CF (at step 522).

Next, the operating frequency of the inverter is limited to apredetermined range of frequencies. The operating period T_(OP), i.e.,T_(BASE)+CF, is determined at step 524 from the present correctionfactor CF. If the operating period T_(OP) is less than a predeterminedminimum period, T_(MIN), i.e., the operating frequency f_(OP) is greaterthan a predetermined maximum frequency, f_(MAX) (at step 525), thecorrection factor CF is set equal to the minimum period T_(MIN) minusthe base operating period T_(BASE), i.e., f_(OP)=1/T_(MIN) (at step526). If the operating period T_(OP), i.e., T_(BASE)+CF, is greater thana predetermined maximum period, T_(MAX), i.e., the operating frequencyf_(OP) is less than a predetermined minimum frequency, f_(MIN) (at step528), the correction factor is set equal to the maximum period T_(MAX)minus the base operating period T_(BASE), i.e., f_(OP)=1/T_(MAX) (atstep 530). Finally, the operating period T_(OP) is set to the baseperiod T_(BASE) Plus the correction factor CF (at step 532).Accordingly, the microprocessor 450 produces the PWM signal 456 at theoperating frequency f_(OP) and operating duty cycle d_(OP).

FIG. 6C is a flowchart of the software executed by the microprocessor450 when the target lamp current I_(TARGET) changes. In response to achange in the target lamp current I_(TARGET) (at step 540), themicroprocessor 450 determines a new base period T_(BASE) (at step 542).The microprocessor 450 may use a predetermined relationship between thetarget lamp current I_(TARGET) and the base operating frequencyf_(BASE), for example, the target ballast operating frequency curve ofFIG. 4, to determine the base operating frequency f_(BASE), and thus thebase operating period T_(BASE) (since T_(BASE)=1/f_(BASE)). Next, themicroprocessor 450 sets the correction factor CF at step 544.Preferably, the microprocessor 450 initially maintains the correctionfactor CF constant (i.e., unchanged) in response to a change in targetlamp current I_(TARGET). Finally, the microprocessor 450 sets the newoperating period T_(OP) at step 546. Accordingly, the new operatingfrequency f_(OP) will initially be offset from the new base frequencyf_(BASE) by the correction factor CF. Alternatively, at step 544, themicroprocessor 450 could set the correction factor CF to a predeterminedvalue, e.g., zero, whenever the target lamp current I_(TARGET) changes.Then, in either case, the microprocessor 450 adaptively modifies theoperating frequency f_(OP) from the base frequency f_(BASE) inaccordance with the method of the present invention as described above.

FIG. 7 shows a plot of the target operating frequency f_(OP) of theballast 400 versus the lamp current according to the present invention.Further, FIG. 7 shows a plot of the operating frequency versus the lampcurrent at both a fixed 50% duty cycle and a fixed 43% duty cycle, i.e.,the preferred target duty cycle. Accordingly, when operating at a givenlamp current (near high-end), the ballast 400 will adaptively shift theoperating frequency f_(OP) to achieve a 43% duty cycle. Near low-end,the operating frequency f_(OP) is limited to the predetermined maximumfrequency f_(MAX).

The predetermined maximum frequency f_(MAX) is selected to be thedesired frequency when operating at low-end. In the present embodiment,at low light levels, the operating duty cycle d_(OP) is less than thepredetermined target duty cycle d_(TARGET) (i.e., 43%) and the operatingfrequency f_(OP) is limited to the predetermined maximum frequencyf_(MAX). As the requested light level (i.e., the target lamp currentI_(TARGET)) is increased, the operating duty cycle d_(OP) is increasedwhile the operating frequency f_(OP) is held constant at thepredetermined maximum frequency f_(MAX). The microprocessor 450eventually reaches a point where the control loop will attempt to drivethe operating duty cycle d_(OP) to be over 43%. At this point, theoperating frequency f_(OP) shifts while the operating duty cycle d_(OP)remains near the preferred target duty cycle d_(TARGET) of 43%.

FIG. 8 is a control system diagram illustrating the control loops forcontrol of the operating frequency f_(OP) and the operating duty cycled_(OP) of the ballast 400 according to the present invention. Both theoperating frequency f_(OP) and the operating duty cycle d_(OP) arecontrolled via closed-loop techniques. As in the prior art ballasts 100,300, the actual lamp current I_(ACTUAL) is provided as feedback to theduty-cycle control loop and is subtracted from the target currentI_(TARGET) to produce a lamp current error signal, e_(l), and thus, viathe compensator, the desired duty cycle signal d_(OP). However, in theballast 400 of the present invention, the desired frequency signalf_(OP) is determined in response to the target lamp current, theoperating duty cycle, and the target duty cycle.

The correction value CF, i.e., the operating frequency f_(OP), isadjusted very slowly with respect to the operating duty cycle d_(OP).This slow adjustment prevents unstable operation that could result ifboth control loops had similar response times (or similar bandwidths).Preferably, the operating duty cycle d_(OP) adjustment operates with aresponse time of 1 msec to 2 msec, i.e., with a bandwidth of 500 Hz to 1kHz, while the operating frequency f_(OP) adjustment operates with aresponse time of 0.7 sec to 1.4 sec, i.e., with a bandwidth of 0.7 Hz to1.4 Hz. Specifically, the response time of the operating frequencyf_(OP) control loop of the ballast 400 is determined by the cycle timeof the frequency adjustment process (of FIGS. 6A and 6B), the size ofthe accumulator ACC, and the values of the maximum duty-cycle errorvalues e_(MAX+), e_(MAX−). Preferably, the operating duty cycle d_(OP)is adjusted at least ten times faster than the operating frequencyf_(OP).

In the event of rapid changes in desired light level, the predeterminedrelationship between the target lamp current I_(TARGET) and the baseoperating frequency f_(BASE), i.e., the target ballast operatingfrequency curve of FIG. 4, gets the operating frequency f_(OP) in theballpark. Then, the adaptive frequency shift routine makes smallcorrections to the operating frequency f_(OP) very slowly without anynoticeable lag in performance. While it is important for themodification of the operating frequency f_(OP) to be slow with respectto the adjustment of the duty cycle d_(OP) to avoid oscillations, theduty cycle control loop must be fast enough to reach the desired lightlevel quickly enough so as to not cause a noticeable lag in dimmingperformance.

Testing has shown that a duty cycle of 43% is sufficient, i.e., highenough, to prevent “mercury pumping” in the lamp 108. The duty cycle of43% is also low enough to allow for dynamic “headroom” (or margin) withrespect to the duty cycle of 50%, which is the maximum duty cycle of theballast 400. Since the correction factor is initially held constant whenthe target light level changes (in the preferred embodiment of thepresent invention), and the operating frequency is adjusted ratherslowly, the operating duty cycle will most likely temporarily rise above43% when the desired light level, i.e., the desired lamp current, isquickly increased. The headroom minimizes the likelihood that the dutycycle will reach 50% and the compensator circuit 216 will saturate.

FIG. 9 is a control system diagram illustrating the control loops of aballast 900 according to a second embodiment of the present invention.The ballast 900 is operable to control the operating frequency of theballast in response to only the operating duty cycle and the target dutycycle. In this embodiment, the ballast 900 is not operable to controlthe operating frequency in dependence upon the target lamp current. Theballast 900 is operable to drive the lamp 108 such that mercury pumpingis avoided. However, when the target lamp current changes, the actuallamp current, and thus the lamp intensity, changes at a slower rate thanin the previous embodiment, since the operating frequency control loop,i.e., the duty cycle error value e_(d), is solely in control of theoperating frequency.

FIG. 10 is a flowchart of the software executed by the microprocessor ofthe ballast 900 to adaptively change the operating frequency f_(OP)according to the second embodiment of the present invention. Steps 1002through 1012 are similar in function to steps 502 through 512 (of FIGS.6A and 6B) executed by the microprocessor 450 of the ballast 400according to the first embodiment of the present invention. The processof FIG. 10 does not utilize either a base period or a correction factorto determine the operating period T_(OP) and the operating frequencyf_(OP).

If the accumulator has reached a predetermined positive level at step1014, then the operating frequency f_(OP) is decreased by apredetermined increment, e.g., preferably 314 Hz, at step 1016 andlimited to a minimum operating frequency f_(MIN), e.g., preferably about45 kHz, at step 1018. Alternatively, if the accumulator has reached apredetermined negative level at step 1020, then the operating frequencyf_(OP) is increased by the predetermined increment, i.e., 314 Hz, atstep 1022 and limited to a maximum operating frequency f_(MAX), e.g.,preferably about 70 kHz, at step 1024. If the accumulator has reachedneither the predetermined positive level nor the predetermined negativelevel, the process exits without changing the operating frequencyf_(OP).

FIG. 11 is a simplified schematic diagram of a ballast 1100 according toa third embodiment of the present invention. The ballast 1100 has anentirely analog control circuit 1110, with a control loop for control ofthe operating duty cycle d_(OP) and another control loop for control ofthe operating frequency f_(OP). The components of the duty cycle controlloop, i.e., the reference circuit 212, the summing circuit 214, and thecompensator circuit 216, operate the same way as those components of theanalog control circuit 210 of the prior art ballast 100 to produce a PWMsignal 1170 characterized by the operating duty cycle d_(OP) and theoperating frequency f_(OP) at the output of the comparator 220.

However, the analog control circuit 1110 uses the operating duty cycled_(OP) as feedback to determine the operating frequency f_(OP). The PWMsignal 1170 is provided to a low pass filter (LPF) 1172 to produce afirst DC reference signal 1174 representative of the duty cycle of thePWM signal 1170. A reference circuit 1176 generates a second DCreference signal 1178, which is representative of the target duty cycled_(TARGET). The first DC reference signal 1174 is subtracted from thesecond DC reference signal 1178 by an adding circuit 1180 to produce aduty cycle error signal 1182. The duty cycle error signal 1182 isprovided to a compensator circuit 1184, which includes an integrator(not shown) and drives a voltage-controlled oscillator (VCO) 1186, e.g.,a triangle wave oscillator. The VCO 1186 produces a triangle wave 1188at a frequency dependent on the voltage provided by the compensatorcircuit 1184. The triangle wave 1188 is compared to the duty cyclerequest voltage 246 by the comparator 220 to produce the PWM signal1170.

The frequency control loop of the analog control circuit 1110 operatesto drive the duty cycle error signal 1182 to zero. Changes in theoperating frequency f_(OP) will result in changes in the current throughthe lamp 108. Accordingly, the duty cycle control loop of the analogcontrol circuit 1110 will change the operating duty cycle d_(OP) toachieve the target lamp current I_(TARGET). Since the ballast 1100controls the operating frequency f_(OP) only in response to theoperating duty cycle d_(OP) and the target duty cycle d_(TARGET), theballast 1100 operates according to the control system diagram of FIG. 9.

Although the present invention has been described in relation toparticular embodiments thereof, many other variations and modificationsand other uses will become apparent to those skilled in the art. It ispreferred, therefore, that the present invention be limited not by thespecific disclosure herein, but only by the appended claims.

1. An electronic ballast for driving a gas discharge lamp, the ballastcomprising: an inverter operable to convert a substantially DC busvoltage to a high-frequency AC voltage having an operating frequency andan operating duty cycle; a resonant tank operable to couple thehigh-frequency AC voltage to the lamp to generate a present lamp currentthrough the lamp; a control circuit operable to control the operatingfrequency and the operating duty cycle of the high-frequency AC voltageof the inverter and operable to receive a target lamp current signalrepresentative of a target lamp current; and a current sense circuitoperable to provide to the control circuit a present lamp current signalrepresentative of the present lamp current; wherein the control circuitis operable to control the operating duty cycle of the high-frequency ACvoltage of the inverter in response to the target lamp current signaland the present lamp current signal; and the control circuit is operableto control the operating frequency of the high-frequency AC voltage ofthe inverter in response to the operating duty cycle and a target dutycycle, such that the control circuit is operable to minimize thedifference between the operating duty cycle and the target duty cycle.2. The electronic ballast of claim 1, wherein the control circuitcomprises a digital portion and an analog portion.
 3. The electronicballast of claim 2, wherein the digital portion comprises amicroprocessor for control of the inverter.
 4. The electronic ballast ofclaim 3, wherein the microprocessor is operable to receive the targetlamp current signal.
 5. The electronic ballast of claim 4, wherein themicroprocessor is operable to control the operating frequency of theinverter to a base operating frequency in response to the target lampcurrent signal, when the target lamp current changes in value.
 6. Theelectronic ballast of claim 4, wherein the microprocessor is operable tocontrol the operating frequency of the inverter to a base operatingfrequency in response to the target lamp current signal in dependenceupon a predetermined relationship between the operating frequency andthe target lamp current.
 7. The electronic ballast of claim 4, whereinthe microprocessor is operable to receive the target lamp current signalfrom a phase-control input.
 8. The electronic ballast of claim 4,wherein the microprocessor is operable to receive the target lampcurrent signal from a digital message received from a communicationlink.
 9. The electronic ballast of claim 3, wherein the analog portioncomprises: a summing circuit operable to generate an error signalrepresentative of the difference between the present lamp current signaland a target lamp current signal representative of the target lampcurrent; and a compensator circuit operable to generate a control signalrepresentative of the operating duty cycle in response to the errorsignal.
 10. The electronic ballast of claim 9, wherein themicroprocessor is operable to provide the target lamp current signalrepresentative of the target lamp current.
 11. The electronic ballast ofclaim 9, wherein the microprocessor comprises an analog-to-digitalconverter for receipt of the control signal generated by the compensatorcircuit.
 12. The electronic ballast of claim 3, wherein themicroprocessor is operable to drive the inverter with a pulse-widthmodulated signal at the operating frequency and the operating dutycycle.
 13. The electronic ballast of claim 1, wherein the controlcircuit comprises an analog control circuit having an operatingfrequency control portion and an operating duty cycle control portion.14. The electronic ballast of claim 13, wherein the operating frequencycontrol portion comprises: a first summing circuit operable to generatea first error signal representative of the difference between theoperating duty cycle and the target duty cycle; a first compensatorcircuit operable to generate a first control signal representative ofthe operating frequency in response to the first error signal; and avoltage-controlled oscillator operable to generate an oscillating signalhaving a frequency dependent on the first control signal.
 15. Theelectronic ballast of claim 14, wherein the operating duty cycle controlportion comprises: a second summing circuit operable to generate asecond error signal representative of the difference between the presentlamp current signal and the target lamp current signal; and a secondcompensator circuit operable to generate a second control signalrepresentative of the operating duty cycle in response to the seconderror signal.
 16. The electronic ballast of claim 15, wherein the analogcontrol circuit further comprises: a comparator operable to compare thefirst control signal and the second control signal and to generate apulse-width modulated signal at the operating frequency and theoperating duty cycle.
 17. The electronic ballast of claim 1, wherein thecontrol circuit is operable to control the operating duty cycle with afirst response time and to control the operating frequency with a secondresponse time substantially greater than the first response time. 18.The electronic ballast of claim 1, wherein the control circuit isoperable to control the operating frequency of the high-frequency ACvoltage of the inverter further in response to the target lamp currentsignal.
 19. The electronic ballast of claim 1, wherein the target dutycycle is about 43%.
 20. A method for controlling an electronic ballastfor driving a gas discharge lamp, the ballast comprising an invertercharacterized by an operating frequency and an operating duty cycle, themethod comprising the steps of: generating a lamp current through thegas discharge lamp in response to the operating frequency and theoperating duty cycle of the inverter; generating a present lamp currentsignal representative of the lamp current through the gas dischargelamp; receiving a target lamp current signal representative of a targetlamp current; controlling the duty cycle of the inverter in response tothe target lamp current signal and the present lamp current signal; andcontrolling the operating frequency of the inverter in response to theoperating duty cycle of the inverter and a target duty cycle, such thatthe difference between the operating duty cycle and the target dutycycle is minimized.
 21. The method of claim 20, further comprising thestep of: generating a duty cycle error value representative of thedifference of the target duty cycle and the operating duty cycle;wherein the step of controlling the operating frequency comprisescontrolling the operating frequency in response to the duty cycle errorvalue, such that the duty cycle error value is minimized.
 22. The methodof claim 21, further comprising the step of: setting the operatingfrequency of the inverter to a base operating frequency, when the targetlamp current changes in value, in dependence upon a predeterminedrelationship between the operating frequency and the target lampcurrent.
 23. The method of claim 22, wherein the operating frequency isdetermined from the base operating frequency and a correction factor.24. The method of claim 23, wherein the correction factor is increasedwhen the duty cycle error value is positive and is decreased when theduty cycle error value is negative.
 25. The method of claim 24, whereinthe operating frequency is limited to a predetermined range offrequencies.
 26. The method of claim 23, wherein the correction factoris changed to a predetermined value when the target lamp current changesin value.
 27. The method of claim 26, wherein the predetermined value iszero.
 28. The method of claim 23, wherein the correction factor isinitially held constant when the target lamp current changes in value.29. The method of claim 21, wherein the operating frequency is decreasedwhen the duty cycle error value is positive and is increased when theduty cycle error value is negative.
 30. The method of claim 29, whereinthe operating frequency is limited to a predetermined range offrequencies.
 31. The method of claim 21, wherein the step of controllingthe operating frequency comprises minimizing the duty cycle error valueonly so long as the duty cycle error value is outside of a dead-band.32. The method of claim 20, further comprising the step of: setting theoperating frequency of the inverter to a base operating frequency independence on the target lamp current signal, when the target lampcurrent changes in value.
 33. The method of claim 20, further comprisingthe step of: generating a current error signal representative of thedifference of the target lamp current signal and the present lampcurrent signal; wherein the step of controlling the duty cycle comprisescontrolling the duty cycle in response to the current error signal, suchthat the current error signal is minimized.
 34. The method of claim 20,wherein the step of adjusting the duty cycle is performed with a firstresponse time and the step of adjusting the operating frequency isperformed with a second response time substantially greater than thefirst response time.
 35. The method of claim 20, wherein the target dutycycle is about 43%.
 36. A control circuit for an electronic ballasthaving an inverter for driving a gas discharge lamp, the control circuitoperable to control an operating frequency and an operating duty cycleof the inverter of the ballast, the control circuit comprising: a dutycycle control portion for controlling the operating duty cycle of theinverter in response to a target lamp current signal and a present lampcurrent signal; and a frequency control portion for controlling theoperating frequency of the inverter in response to the operating dutycycle and a target duty cycle; wherein the frequency control portion isoperable to minimize the difference between the operating duty cycle andthe target duty cycle.
 37. The control circuit of claim 36, wherein thefrequency control portion is further operable to control the operatingfrequency in response to the target lamp current signal.
 38. The controlcircuit of claim 37, wherein the frequency control portion is responsiveto a duty cycle error signal representative of the difference betweenthe operating duty cycle and the target duty cycle.
 39. The controlcircuit of claim 38, wherein the duty cycle control portion isresponsive to a lamp current error signal representative of thedifference between the present lamp current signal and the target lampcurrent signal.
 40. The control circuit of claim 36, wherein the dutycycle control portion operates with a first response time and thefrequency control portion operates with a second response timesubstantially greater that the first response time.
 41. An electronicballast for driving a gas discharge lamp, the ballast comprising: aninverter operable to convert a substantially DC bus voltage to ahigh-frequency AC voltage having an operating frequency and an operatingduty cycle; a resonant tank operable to couple the high-frequency ACvoltage to the lamp to generate a present lamp current through the lamp;a control circuit operable to control the operating frequency and theoperating duty cycle of the high-frequency AC voltage of the inverterand operable to receive a target lamp current signal representative of atarget lamp current; and a current sense circuit operable to provide tothe control circuit a signal representative of the present lamp current;wherein the control circuit is operable to control the operatingfrequency to a base operating frequency in dependence on the target lampcurrent signal, when the target lamp current changes in value; tocontrol the operating duty cycle in response to a target lamp currentsignal and the present lamp current signal; and to control the operatingfrequency in response the operating duty cycle and a target duty cycle,such that the control circuit is operable to minimize the differencebetween the operating duty cycle and the target duty cycle.